When fabricating integrated circuits, layers of insulating, conducting, and semiconducting materials are deposited and patterned to produce desired structures. Interconnect “back end” metallization processes include via formation and metal line or wire formation. Via formation vertically connects conductive layers through an insulating layer. Conventionally, contact vias or openings are formed in the insulating layer, such as, PECVD deposited oxide (k=4) formed from tetraethylorthosilicate (TEOS) precursors and PECVD or high density plasma (HDP) deposited fluorinated oxide (FSG) (k=3.4-3.7). The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring above and below the insulating layers. The layers interconnected by vertical vias typically include horizontal metal lines running across the integrated circuit. Such lines are conventionally formed by depositing a metal layer, such as aluminum, over the insulating layer, masking the metal layer in a desired wiring pattern, and etching away metal between the desired wires or conductive lines.
Damascene processing involves forming trenches in the pattern of the desired lines, filling or overfilling the trenches with a metal or other conductive material, and then CMP polishing the metal and stopping on the insulating layer. Wires are thus left within the trenches, isolated from one another in the desired pattern. Recent copper metallization processes, for example, typically employ damascene processing.
In an extension of damascene processing, a process known as dual damascene involves forming two insulating layers, typically separated by an etch stop material (see FIG. 1, described below), and forming trenches in the upper insulating layer, as described above for damascene processing. Of course, there are also alternative approaches available. In some embodiments, one deposits the insulating dielectric in one step without an etch stop layer (see FIG. 2, described below) and forms the trenches in the single insulating layer by performing a timed etch. After the trenches have been etched, a further mask can be employed to etch contact vias downwardly through the floor of the trenches and the lower insulating layer to expose lower conductive elements where contacts are desired. As will be appreciated by one of skill in the art, there are alternative approaches for making the structures as well. For example, the structure can be made in reverse by the via-first trench last (VFTL) approach with a timed etch for the overlying trenches.
Conductive elements, such as capacitors, contacts, runners and wiring layers, must each be electrically isolated from one another for proper integrated circuit operation. In addition to providing insulating layers around such conductive elements, care must be taken to prevent diffusion and spiking of conductive materials through the insulating layers, which can cause undesired short circuits among devices and lines. Protective barriers are often formed between via or trench walls and metals in a substrate assembly to aid in confining metal within the via or trench walls. Barriers are thus useful for damascene and dual damascene interconnect applications, particularly for fast-diffusing elements such as copper.
Candidate materials for protective barriers should foremost exhibit effective diffusion barrier properties. Additionally, the materials should demonstrate good adhesion with adjacent materials (e.g., oxide via walls, adhesion layers, etch stop layers and/or metallic materials that fill the vias and trenches). For many applications, a barrier layer is positioned in a current flow path and so is conductive. Typically, barriers have been formed of metal nitrides (MNx), such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), which are dense and adequately conductive for lining contact vias, wiring trenches, and other conductive barrier applications.
These lined vias or trenches are then filled with metal by any of a variety of processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and electroplating. For effective conductivity and to avoid poor electro-migration during operation, the metal of a contact or wiring layer should fill the via or trench without leaving voids or key holes. Completely filling deep, narrow openings with conductive material is becoming ever more challenging as integrated circuit dimensions are constantly scaled down in pursuit of faster operational processing speeds and lower power consumption.
As illustrated in FIGS. 1 and 2, utilizing a conductive barrier layer and/or other liners makes filling the trenches and vias of dual damascene processing even more difficult. FIG. 1 illustrates a dual damascene process in which an upper insulating layer 10 is formed over a lower insulating layer 12, which is in turn formed over a conductive wiring layer 14, preferably with an intervening dielectric diffusion barrier 15. This dielectric barrier 15 serves to prevent copper or other conductive material of the underlying metal 14 from diffusing into the overlying dielectric layer 12.
A mask is employed to pattern and etch trenches 16 in a desired wiring pattern. In the illustrated embodiment, the trench 16 is etched down to the level of an etch stop layer 19, which is formed between the two insulating layers 10, 12. This etch stop layer 19 is typically patterned and etched, prior to deposition of the upper insulating layer 10, to form a buried hard mask that defines horizontal dimensions of desired contact vias that are to extend from the bottom of the trench 16. Continued etching through the hard mask 19 opens a contact via 20 from the bottom of the trench 16 to the lower conductive wiring layer 14. FIG. 1 also shows an upper etch stop or chemical mechanical polishing (CMP) stop layer 21 over the upper insulating layer 10 to stop a later planarization step, as will be appreciated by the skilled artisan. As noted above, this is merely one method of forming dual damascene trenches and vias. In other embodiments, a VFTL (via-first, trench-last) approach can be used with a timed etch instead of employing an etch stop layer. This scheme is demonstrated in FIG. 2, in which CMP stop and buried hard masks are omitted.
After removing photoresist, residue removal and/or other cleaning steps, protective liners 22, preferably formed of conductive material, are then formed on the exposed horizontal and sidewall surfaces. Typically, the liners 22 at least include a metal nitride, and may additionally include adhesion enhancing and seeding layers. For example, the liner 22 can comprise a tri-layer of Ti/TiN/Cu. In such a structure, the titanium layer serves to improve adhesion with exposed oxide sidewalls; the titanium nitride serves as a diffusion barrier; and a thin copper layer serves as a seed for later electroplating of copper. In other examples, the liners 22 can include tantalum nitride or tungsten nitride barriers. The skilled artisan will appreciate that other barrier materials can also be employed.
Conformal deposition of the liners 22, however, is very difficult with conventional processing. For example, physical vapor deposition (PVD), such as sputtering, of a metal layer (for adhesion, barrier and/or seed layer) requires thickness of at least about 50 Å over all surfaces of the trench 16 and contact via 20. Unfortunately, PVD of metal into high aspect ratio voids necessitates much greater deposition on the top surfaces of the workpiece to produce adequate coverage of the via bottom. For example, some state-of-the-art trench and contact structures for dual damascene schemes require about 150-250 Å PVD metal in order for 50 Å of metal to reach the bottom and sidewalls of the contact via 20. Some schemes have required as much as 500 Å PVD metal in order for 50 Å of metal to reach the bottom and sidewalls of the contact via 20.
This poor step coverage is a result of the high aspect ratio of voids formed for dual damascene processing in today's integrated circuits. The aspect ratio of a contact via is defined as the ratio of depth or height to width. In the case of dual damascene contacts, the trench 16 and contact via 20 together reach through two levels of insulating layers 10, 12, such that the effective aspect ratio of the via 20 is very high.
Conventional deposition processes produce very poor step coverage (i.e., the ratio of sidewall coverage to field or horizontal surface coverage) of such high aspect ratio vias for a variety of reasons. Due to the directionality of PVD techniques, for example, deposition tends to accumulate more rapidly at upper corners 26 of the trench 16 and upper corners 28 of the via 20, as compared to the via bottom 30. As a result of the rapid build-up of deposited material on the upper surfaces of the structure, the lining layers occupy much of the conductive line width in the trench 16 and even more, proportionately, of the contact via 20. These built-up corners 26, 28 then cast a shadow into the lower reaches of the structure, such that lower surfaces, and particularly lower corners, are sheltered from further deposition. Although PVD deposition can be directed more specifically to the via bottom, e.g., by collimation or by ionization of the depositing vapor, such additional directionality tends to sacrifice sidewall coverage.
Chemical vapor deposition (CVD) processes have been developed for certain metals and metal nitrides. CVD tends to exhibit better step coverage than PVD processes. In order for CVD processes to exhibit good step coverage, the reaction must be operated in the so-called “surface controlled” regime. In this regime, reaction species do not adhere to trench or via walls upon initial impingement. Rather, the species bounce off trench/via surfaces several times (e.g., 10-500 times) before reacting.
State-of-the-art CVD processes for depositing barrier layers at temperatures sufficiently low to be compatible with surrounding materials do not operate completely within the surface-controlled regime. Accordingly, even CVD processes tend to deposit far less material at the bottom of a dual damascene contact via 20 then on the upper surfaces and sidewalls of the structure. The upper corners of the trench 16 and the contact via 20 represent a high concentration of surface area to volume. Deposition upon the horizontal upper surfaces and adjacent vertical sidewall surfaces merge together to result in an increased deposition rate near the corners 26, 28. Additionally, flowing reactants diffuse slowly into the confined spaces of the trench 16 and contact via 20. Accordingly, the concentration of reactants reaching the via bottom 30 is far reduced relative to the concentration of reactants reaching upper surfaces of the structure. Thus, while somewhat improved relative to PVD, CVD step coverage of dual damascene structures remains uneven with most currently known low temperature CVD techniques.
In the pursuit of devices with faster operational speeds and lower power consumption, dimensions within integrated circuits are constantly being scaled down. With continued scaling, the aspect ratio of contacts and trenches continues to increase. This is due to the fact that, while the width or horizontal dimensions of structures in integrated circuits continues to shrink, the thickness of insulating layers separating metal layers cannot be commensurately reduced. Reduction of the thickness in the insulating layers is limited by the phenomenon of parasitic capacitance, whereby charged carriers are slowed down or tied up by capacitance across dielectric layers sandwiched by conductive wires. As is known, such parasitic capacitance would become disabling if the insulating layer were made proportionately thinner as horizontal dimensions are scaled down.
With reference to FIG. 2, a scaled-down version of FIG. 1 is depicted, wherein like parts are referenced by like numerals with the addition of the suffix “a.” FIG. 2 also differs from FIG. 1 in illustrating a dual damascene scheme without a buried hard mask on etch stop layer and without an upper CMP stop. As shown, continued scaling leads to a more pronounced effect of uneven step coverage while lining dual damascene structures. Material build-up at the corners 28a of the contact via 20a quickly reduces the size of the opening, even further reducing the concentration of reactants that reach into the contact via 20a. Accordingly, coverage of the via bottom surface 30a drops off even faster. Moreover, the percentage of the trench 16a occupied by the liner (e.g., barrier) materials is much greater for the scaled down structure of FIG. 2. Since the lining material is typically less conductive than the subsequent filler metal (e.g., copper), overall conductivity is reduced. Worse yet, cusps at the corners 28a of the contact via can pinch off before the bottom 30a is sufficiently covered, or during deposition of the filler metal.
Independently of efforts to improve barrier film uniformity are efforts to reduce the dielectric or permittivity constant (k) value of the interlevel dielectric (ILD) material. A reduced dielectric constant value results in less parasitic capacitance per unit thickness of the ILD, such that for a given circuit design tolerance for parasitic capacitance, a so-called “low k” material can provide a thinner ILD. “Low k” designates a material with a k value below that of silicon oxide (k≈4) and fluorinated silicate glass (FSG) (k≈3.4-3.7), the currently predominant ILD material in integrated circuit fabrication. Accordingly, the aspect ratio of contacts and trenches to be filled can be reduced and lining these openings becomes easier.
A variety of materials and techniques are being developed for producing low k films in integrated circuits. Deposition methods currently include spin-on deposition, CVD, plasma enhanced CVD (PECVD) and high density plasma (HDP) CVD, depending upon the characteristics desired. Some of the methods and films have been described by Laura Peters, “Pursuing the Perfect Low-k Dielectric” Semiconductor International, Vol. 21, No. 10 (September 1998), and the references cited therein. Some films have a k value from 3 to 3.5 such as hydrogen silsesquioxane (HSQ) and fluorinated oxides (FSG). Organic polymers, such as benzoncyclobutene (BCB) and polyarylene ethers (PAE), exhibit even lower k values between 2.5 and 3 range. Other work with polytetrafluoroethylene (PTFE) using spin-on techniques has achieved intrinsic k values of about 1.9. ASM Japan K.K. has developed low k materials formed by plasma enhanced CVD, including low-k, ultra low-k (ULK, which can be porous or non-porous) and extreme low-k (ELK, which is generally porous) materials. Other companies have created nanoporous inorganic-organic hybrids.
Use of such low k materials as an ILD in an integrated circuit will considerably reduce the aspect ratios of openings in the ILD because one can make the openings thinner for a given tolerable parasite capacitance. Accordingly, lining such openings with adequate conformality should prove simpler as compared with lining openings with higher aspect ratios.
Integrating these new materials with existing technologies, however, introduces its own challenges. Among other requirements, low k films exhibit sufficiently high chemical, thermal and mechanical stability in the face of disparate adjacent materials and exposure to a variety of processing environments. ILD materials should be compatible with etching, deposition, cleaning and polishing processes in order to integrate reliably with a manufacturing process. As will be appreciated by the skilled artisan, integration of new materials and processes into established process flows is rarely a straightforward matter, as evidenced by complications arising from the introduction of copper lines into state-of-the-art integrated circuit designs.
It would accordingly be advantageous to provide low k material without changing the material characteristics of the ILD with each succeeding generation. One manner in which the k value of a material can be lowered without changing the material properties of the ILD is to make the material porous. In effect, porous dielectrics combine the dielectric strength of air (k≈1.0) with that of the dielectric material in which the pores are formed. Advantageously, the k value of a porous material is “tunable” in the sense that the k value can be altered without introducing new materials by changing the porosity of a material that has already been integrated.
Currently silicon oxide (k≈4) is widely used in process flows. Porous versions of silicon oxide or “silica” can have both a low k value and compatibility with current process flows. This has led to the development of classes of porous silica known as nanogels, aerogels, xerogels and mesogels. Similarly, newer low k materials, once integrated into process flows, can have their k values tuned by adjusting porosity of the low k material. With low k materials currently under development, it appears that achieving k values below 2.5 will likely involve providing a porous insulating material.
Lining such materials, in an effective manner, is not a simple process. Although CVD and PVD may adequately line a low aspect ratio opening, non-conformality of conventional deposition techniques can still be problematic. Also, as the interconnect dimensions are shrinking, the percentage of copper with respect to barrier in the vias is not shrinking, thereby increasing via resistance. Atomic layer deposition (ALD) can be helpful in overcoming some of the problems presented by CVD and PVD processes (see, U.S. Pat. No. 6,482,733, issued Nov. 19, 2002, and U.S. Pat. No: 6,759,325, issued Jul. 6, 2004 herein incorporated by reference in their entireties). However, some embodiments disclosed previously can still have difficulties with adhesion, shorting, and general failure. Moreover, many of these previous approaches employed adding additional layers to the insulating layer, which will reduce the volume of copper that can later be introduced into the vias and trenches.